ENCASIT, which stands for European Network for the Co-ordination of Advanced System Integration Technologies, is a Co-ordinated Action funded by the 6th Framework of the European Commission.

Its objectives are to extend the activities that were carried out by GOOD-DIE / ENCAST and not just cover KGD but all aspects of system integration, manufacture, assembly, packaging and test. These will include wafer scale packaging, stacked die and packages, SiP, SOC, flip chip, MEMS etc. and all aspects of assembly, test and reliability.

ABSTRACT

The objective of ENCASIT is to organise a Network under the umbrella of a Coordination Action, to gather and disseminate information related to Systems Integration and System in a Package, for various types of technologies including Semiconductor, MEMs, Nano- Bio- etc. in a variety of mass-market applications of importance to European industry. Attention will also be given to applicability of such technologies to high temperature applications and also the issue of Whole Life Support. Typical technologies to be monitored include waferscale packaging, 3D packaging, SiP, SOP, MCM, stacked packages, and integration of other technologies such as MEMs, Nano, Bio and Fluidics to electronic sub assemblies. This will be carried out by organising workshops and meetings on the above technologies and disseminating the information via a regularly published newsletter and on a web site freely accessable to the semiconductor and microelectronics enginnering community. Information will also be gathered and disseminated by the same method by attending other workshops, conferences, meetings, etc. worldwide.

Roadmaps in the relevant technogies will be monitored and assessed for System Integration methodologies and new Roadmaps will be proposed where appropriate. Standards related to Si and SiP, will pursued by participation in the IEC TC47 working group producing the IEC 62258 standard and other standards groups. An International workshop, CAST 2007, will be organised and there will be coordination with other groups such as, NEXUS, SEMI Europe, Jisso European, USA and Japan, and the DPC KGD workshop in the USA. Also work will continue in expanding a Die Products User Club to assist SME's in the use of these components and technologies in Europe.

OBJECTIVES

	To monitor activities in System Integration of various technologies combining micro-, nano-, photo, bio-, MEMs, etc. and to Roadmap how System Integration will develop, especially for System in a Package (SiP) technologies.
	To monitor activities in System Integration and design for High Temperature and Harsh Environments and to Roadmap how component and integration technologies will develop to address the requirements of these applications.
	To work with IEC/PT62258 committee and other standards committees in the preparation of standards that support the System Integration infrastructure. This will enable Europe to understand all the requirements correct design, simulation, assembly and test can be carried out to produce miniaturised reliable systems. In short, to deliver the required contribution, through the standardization and dissemination efforts, for the fundamental building blocks for the “e-technologies”.
	To organise workshops on the technologies on electronic system miniaturization and system in a package (SiP), on specific topics, hosted by major organisations in Europe such as IMEC, Infineon, Philips, AMIS, Bosch etc. Topics that may be covered include test, SiP design, MEMS, Nano- and Bio- technology, user experience, assembly, storage, high temp applications etc.
	To attend workshops and conferences put on by other organisations worldwide such as JISSO, SEMI, IMAPS, IEEE etc. and publish the information gathered from these events.
	To be fully involved with the organisation of the Napa KGD and test workshop organised by the DPC each year in September.
	To maintain technical contact with organisations in the Far East such as ASET in Japan and GJ Technologies in China and disseminate information of their activities in Europe.
	To cooperate with the organisations associated with MEMS such as NEXUS, , SEMI Europe etc. to feed them information on the semiconductor industry and to disseminate information developed by themselves through the newsletter and web site.
	To organize and publish a newsletter, at least twice a year, of all the information gathered by ENCASIT, and also publish the information on the web site. The site will also have links to all other major activities worldwide concerned with the technology.
	To co-operate with organisations associated with Whole Life Support of microelectronics such as COG and to disseminate information through workshops and conferences and through the newsletter and web site etc.
	To run a USER Club to help SMEs gain access to the support infrastructure for systems integration and miniaturisation, and to help promote the services they offer in this area.
	To participate in the organisation of the Annual KGD and Test Workshop organised by the Die Products Consortium.
	To investigate the possibilities to become self-supporting through the income generated from the different service activities offered during the ENCASIT coordination action.

STATE-OF-THE-ART

Semiconductor technology is now advancing very rapidly with sub-micron technologies of 0.18 µm, 0.13 µm and now 0.08 µm silicon and 300 mm wafers now in regular production. Waferscale packaging is also now becoming a production issue where the die is protected and can be assembled in conventional SMT production lines.

Other areas of development are the SOC and SiP technologies. SOC is now only considered viable for long production runs as design changes etc. are expensive. SiP is an important technology for time-to-market where quick turn around is required and design changes can be made quickly and has the advantage of maintaining the same footprint. Within theses MCM systems there are now emerging stacking technologies where die are stacked up to or greater than four high or packages are being stacked. This has brought new techniques into the wafer manufacturing arena such as wafer thinning to maintain low profile packages with greatly increased integration.

Another area of advancement is for die to operate at higher temperatures particularly in the automotive and down-hole industries. Here junction temperatures of up to 150ºC or even 200ºC are being required.

The use of MEMS is now becoming an important related industry to the semiconductor industry. Besides the main areas of ink jet heads and air bag sensors many more applications are emerging. These include medical, fluidic, RF and opto applications. Here the need is to integrate these new technologies with the conventional IC packaging technologies. Packaging of these components is one of the main concerns of this technology and at present is given little attention until the last part of the design instead of design for manufacture.

Another key area are the WEEE and RoHS initiatives with the particular reference to the removal of lead from solders in electronic packaging. Currently the high tin, silver copper alloy is the leading alternative and this will be monitored as the change over occurs.

As a Network in a Coordination Action the effort of the members of ENCASIT will be to follow such developments in the state-of-the-art by monitoring through various, workshops, conferences, magazine articles, personal contacts, company visits and other associated projects and networks and disseminating the information via workshops organised by the network, a regularly published newsletter to a circulation of over 1.700 engineers and interested people in Europe and the rest of the world and through the network web site.